In mobile communication networks, the radio interface comprises layers 1 and 2 of the Open System Interconnection (OSI) reference model. Layer 1 is also called physical layer, while layer 2 is sometimes referred to as link layer. Mapping between transport channels and physical channels, spreading and modulation operations, power control and handover mechanisms are typical layer 1 functions. Layer 2 functions, on the other hand, provide the means to transfer data between network entities and to detect (and possibly correct) errors that may occur in layer 1.
In the specifications of modern Radio Access Networks (RANs), such as the Universal Mobile Telecommunication Services (UMTS) Terrestrial RAN (UTRAN) and its Long-Term Evolution (LTE) extension, layer 2 is split into several sub-layers. Each sub25 layer is defined by a dedicated radio interface protocol, including the Medium Access Control (MAC) protocol, the Radio Link Control (RLC) protocol and the Packet Data Convergence Protocol (PDCP). In brief, MAC processing includes mapping between logical channels and transport channels and error correction, RLC processing provides segmentation, concatenation and retransmission services, and PDCP processing comprises compression operations and access stratum 30 security procedures.
Radio interface processing in an exemplary LTE-compliant network entity having a layered protocol stack as shown in FIG. 1 will now be discussed in more detail for the downlink direction in a receiving entity (such as a mobile terminal). In a first step, layer 1 functions (“PHY” layer 6 in FIG. 1) recover 0, 1 or more LTE Transport Blocks (TBs) per Transmission Time Interval (TTI) from the physical channels and deliver the recovered TBs via their associated transport channels to a MAC sub-layer 8. Functions on the MAC sub-layer 8 de-multiplex the transport channels and construct RLC Protocol Data Units (PDUs) from the received TBs. The RLC PDUs are then delivered from the MAC sub-layer 8 to an RLC sub-layer 10 on their associated logical channels, such as the Dedicated Control Channel (DCCH) and the Dedicated Traffic Channel (DTCH).
FIG. 2 illustrates the processing operations performed on the RLC sub-layer 10 and on an PDCP sub-layer 12 of FIG. 1 upon receipt of the RLC PDUs via the DCCH/DTCH in the Acknowledged Mode (AM) of the RLC sub-layer 10. The RLC sub-layer 10 and the PDCP sub-layer 12 belong to a layer 2 processing system of the LTE-compliant network entity.
On the RLC sub-layer 10, the RLC PDUs are received by a function 16 in charge of detecting (and discarding) duplicates of the received RLC PDUs before storing them in a reception and reordering buffer (not shown in FIG. 2). After a reordering function 18 of the RLC sub-layer 10 has reordered the buffered RLC PDUs, a loss detection function 20 analyses the reordered RLC PDUs to detect if any RLC PDU is missing. In the case of a missing RLC PDU, a reordering timer is started, and a STATUS Control PDU indicating the one or more missing RLC PDUs is sent in the uplink to trigger a retransmission.
The in-sequence RLC PDUs are moved from the reception and reordering buffer to a reassembly function 22. The reassembly function 22 processes the buffered in-sequence RLC PDUs to reassemble RLC Service Data Units (SDUs). A delivery function 24 then reads the reassembled RLC SDUs from the reassembly buffer and delivers them in sequence via an AM Service Access Point (AM-SAP) interface 26 to the PDCP sub-layer 12 as illustrated in FIG. 2.
On the PDCP sub-layer 12, the in-sequence RLC SDUs are received by a header removal function 28 in charge of removing the PDCP header from each RLC SDU to recover a PDCP SDU if possible. The following functions performed on the PDCP sub-layer 12 depend on whether or not the higher layer data packets are in fact associated with PDCP SDUs. In case PDCP SDUs can be recovered from the RLC PDUs, the PDCP SDUs are in a first step deciphered by a ciphering function 30 and then (in case of control plane processing only) subjected to an integrity protection operation performed by an integrity protection function 32.
The data packets corresponding to the deciphered user plane PDCP SDUs as well as the user plane data packets not associated with PDCP SDUs are then sent to an decompression function 34 for a decompression of the data packet headers. A subsequent reordering function 36 delivers the data packets with decompressed headers via a PDCP SAP interface 40 to higher protocol layers 42.
In the exemplary LTE scenario illustrated in FIGS. 1 and 2, the layer 2 functions generally have to complete their processing operation triggered in one TTI (of 1 ms) within 1 ms. Assuming an RLC receiving window size of for example 32 ms, it may happen that one RLC SDU is still missing while all RLC SDUs of the next 31 TTIs have already been received. As the delivery function 24 of the RLC sub-layer 10 is configured to deliver the RLC SDUs in sequence to the PDCP sub-layer 12, the 31 RLC SDUs already received are delivered to the PDCP sub-layer 12 only when the single missing RLC SDU is received (or when the RLC reordering window is outdated upon expiry of a timer). In such a case, all RLC SDUs received within the last 32 ms will have to be processed by the PDCP functions within the predefined processing window of 1 ms. Because of the resulting processing peak, the system architecture has to be designed with sufficient hardware resources.
As an example, the ciphering function 30 must have the capability of deciphering 3.2 Gbit/s for an average downlink data rate of 100 Mbit/s. A layer 2 processor executing the ciphering function 30 will thus have to be over-dimensioned from the viewpoint of the average ciphering load. Needless to say that the resulting over-dimensioning significantly adds to the hardware cost of the layer 2 processing system.
The above processing scenario also necessitates an over-dimensioning of an interface between the layer 2 processor and a memory for storing the layer 2 data. For an average downlink data rate of 100 Mbit/s, the memory interface needs in an exemplary deployment the capability of handling a peak data rate of 9.6 Gbit/s within 1 ms. Such a high peak data rate is particularly costly to achieve in a system architecture relying on an external memory. FIG. 3 illustrates such an architecture of a layer 2 processing system comprising a circuit chip 50 and an external memory 52 coupled to a layer 2 processor 54 on the circuit chip 50 via an External Memory Interface (EMIF) 56.
In the exemplary architecture illustrated in FIG. 3, the layer 2 processor 54 accesses the EMIF 56 via an interconnect or bus 57, to which further processing components requiring access to the external memory 52 may be connected. Compared to internal memory interfaces, the EMIF 56 with the capability of handling a peak data rate of 9.6 Gbit/s is much costlier. On the other hand, the apparently obvious solution of replacing the external memory 52 with an on-chip memory is likewise costly for typical memory sizes of several Mbytes.